1. Field of the Invention
The present invention relates to flip-flop and latch circuitry. More particularly, the present invention relates to circuitry which may alternatively provide the function of a latch or a D-type flip-flop.
2. Description of the Related Art
For circuitry of programmable logic devices (PLDs), field programmable gate arrays (FPGAs), microprocessors and other circuits, it may be desirable to have a circuit which at some times functions as a latch, while at other times functions as a D-type flip-flop. Although circuitry may be connected so that specific circuitry for a latch or a D-type flip-flop can be included in a signal path, the circuit which is not selected will provide a wasted resource.
FIG. 1 shows typical components utilized in a D-type flip-flop circuit. The circuitry includes two latches 102 and 104 connected in series. The /Q output of latch 102 is connected to the data input of latch 104 and the clock input of latch 102 is inverted from the clock input of latch 104 to form a D-type flip-flop.
FIG. 2 shows typical circuitry for the latches 102 and 104 of FIG. 1. As shown, the typical latch includes an inverter 200 with its output forming the /Q output of the latch. The latch also includes an inverter 202 with its output connected to the input of inverter 200 and its input connected to the Q output. Transistors in inverter 202 are further weaker than in inverter 200. A data signal is provided to the Q input of the latch 200,202 through a latch pass gate 204 which receives the clock signal at its gate.
To selectively enable provision of a latch or D-type flip-flop, additional pass gates 300 and 302 may be included in the circuitry of FIG. 2, as shown in FIG. 3. Additional pass gate 300 has its gate controlled to provide Vcc to the clock input of latch 102. This puts it in a transparent mode so that latch 104 will function as a standard latch controlled by the inverted clock signal so that it is transparent when the clock is low and will latch the data when the clock signal is high. When pass gate 302 is controlled by its gate signal to be on so that pass gate 300 is off, then the circuit functions as a standard D flip-flop because pass gate 302 will bring the clock signal to the clock input of latch 102.
Using the circuit of FIG. 3, with a latch mode selected, latches 102 provides a wasted resource, unnecessarily occupying chip space. Additional chip space is also required for pass gates 300 and 302 to enable selection of a latch or a D-type flip-flop mode of operation. Such additional circuitry is not desirable.